Modern computing, networking, communications, and other technologies can require several streams of data to be transmitted across a single medium during the same time period. Multiplexing can effectuate such transmission, such as where multiple streams of data at a particular data rate are combined into a single stream of data at a higher data rate.
A conventional two-to-one multiplexer is shown in Prior Art FIG. 1. In this multiplexer, two data streams, labeled D1 and D2, are combined into a single data stream by a selector 101. Selector 101 is operated (e.g., controlled) by a clock signal, labeled CLK in the diagram. When clock CLK is at a low logic level, the data signal D1 is passed to the output line, labeled D3. When the signal CLK is high, the data signal D2 is passed to the output line D3. Thus, the output line alternates between signals D1 and D2, and the two input data signals are combined into a single data stream.
To maintain the integrity of the output data, it is desirable for signal D1 to be stable during the interval when CLK is low. For this reason, the data signal D1 is provided by a first data latch 102, whose output only changes after each rising edge of CLK. This timing relationship is illustrated in timing diagram 103, which shows that transitions 106 of the data signal D1 occur in response to each rising edge of the CLK signal. Provided that the transitions in data signal D1 are completed before the falling edge of CLK, D1 is stable during intervals when the CLK signal is low. This condition will be satisfied provided the clock-to-data delay (sometimes called “clock-to-Q” delay) of data latch 102 is less than half of the repetition period of the CLK signal.
Similarly, when CLK is high, it is desirable for signal D2 to be stable. To achieve this, D2 is provided by a second data latch 104, whose output only transitions in response to each falling edge of CLK, with the requirement that the transition be completed prior to the rising edge of CLK. This timing relationship is also illustrated in the timing diagram 103. A third latch 109 delays D2 by one half clock cycle, relative to D1. In the present discussion, the term “latch” refers to either a latch or a flip-flop. A flip-flop can comprise two intercoupled, co-operational latches. As used herein, the term can refer to other logic circuit elements as well.
Conventional multiplexer 101 can be subject to an operating limitation at high frequencies. At high frequencies, the delay between the rising edge of CLK and a data transition on signal D1 can become comparable to or greater than half of the clock period. If such a condition occurs, the falling edge 105 of CLK, which marks the beginning of the CLK low period, may arrive before the transition 106 in data signal D1 is complete. Such a situation would violate the desired condition that D1 be stable while the CLK signal is low. This violation can cause the output data D3 to be corrupted.
A similar problem can occur on the rising edge of the clock signal if the delay of data latch 104 becomes correspondingly too long. In this case, the data signal D2 may still be in transition when clock signal CLK is high, which can also cause the output data D3 to be corrupted.
The delay from clock-to-data in a data latch, sometimes referred to as “clock-to-Q delay,” can depend on operational, pre-operational, environmental, and other variables. Such variables can include, but are not limited to, variations in temperature, power supply voltage, manufacturing process, and fabrication. These variables can subject the performance of the multiplexer to variations that are not well controlled, and which can be undesirable. For example, a multiplexer that functions adequately at room temperature and nominal supply voltage may exhibit corrupt output data (e.g., fail to function adequately) at elevated temperature or reduced voltage.